`timescale 1ns / 1ps

`define sim 
module pll_rst(

    output  wire    stop            ,
    input   wire    f_adj           ,
	input	wire	clk_50m			,
	input	wire    rst_n  			,
	output  wire    add_en          ,    
	output  reg     sys_rst_n  = 0  ,
	output  wire    sys_clk_p	    ,
	output  wire    dac_clk_n	
    
    );
    
    wire locked ;
   
    always @ (posedge sys_clk_p)
        
        sys_rst_n <=  locked   ; 
        
    reg [8:0]  cnt_1 = 0 ;
    reg [8:0]  cnt_2 = 0 ;
    
    
    always @ ( posedge sys_clk_p )    
    begin
        if (~sys_rst_n )
            cnt_1 <= 0 ;
        else begin 
                if ( cnt_1<499)
                    cnt_1 <= cnt_1 + 1  ;
                else     
                    cnt_1 <=   0      ;     
            end     
    end        
             
    always @ ( posedge sys_clk_p )    
    begin
        if (~sys_rst_n )
            cnt_2 <= 0 ;
        else begin 
                if ( cnt_2 <49 )
                    cnt_2  <= cnt_2 + 1 ;
                else     
                    cnt_2 <=   0        ;     
        end     
    end
    
    
    reg     add_en_1   = 0  ;
    reg     add_en_2   = 0  ;
    
   
    always @ ( posedge sys_clk_p )
    
    begin 
        if ( ~sys_rst_n)
            begin 
                add_en_1   <= 0  ;
                add_en_2   <= 0  ;
            end 
        else begin 
            add_en_1   <= cnt_1== 499  ;             
            add_en_2   <= cnt_2== 49   ;

        end         
               
    end 
 

   wire f_flag     ;
   reg  f_sel  = 0 ;
   
   always @ ( posedge sys_clk_p  )
    begin 
        if ( ~sys_rst_n)
            f_sel <= 0   ;
        else begin 
           if ( f_flag  )
                f_sel <=f_sel +1 ; 
            else 
                f_sel <=f_sel ; 

        end         
               
    end 


  assign    add_en =  f_sel? add_en_2 : add_en_1 ;
       

 
 
     key_process key_process_inst3(    
        .clk         ( sys_clk_p            ) ,
        .rst_n       ( sys_rst_n            ) ,    
        .key_switch  ( f_adj                ) ,   
        .flag_switch ( f_flag               )    
    );  
  
    
    assign  stop =      0 ;
    
                     		
   pll	pll_inst (
		.areset  	( rst_n 	   ),
		.inclk0  	( clk_50m 	   ),
        
        `ifdef sim		
        .c2 	    ( sys_clk_p    ),
        `else    
        .c0 	    ( sys_clk_p    ),
        
        `endif 
		.c1 	    ( dac_clk_n	   ),
       
        
		.locked  	( locked       )
	);
   
		
endmodule
